Technical Field
The instant disclosure relates to a converting technology between ana
log and digital, and particularly relates to a successive approximation register analog-to-digital converting circuit and method thereof.
Related Art
There are multiple types of analog-to-digital converter (ADC) architectures, and these types of architectures have their own advantages. Specifically, the successive approximation register (SAR) ADC has the advantages of low power consumption, small area, and low cost, in comparison with other architecture, so that the SAR ADC is widely applied to different electronic apparatuses.
Along with the improvement in the architecture and manufacturing, the SAR ADC is developed in high speed application; especially the timing-interleaved (TI) SAR ADC architecture is widely utilized. The SAR ADC adopts a binary search algorithm to obtain a digital output code matching an input signal, therefore, the bit-cycling clock of the SAR ADC needs to be higher than the sampling frequency. Generally, the conversion rate of the SAR ADC is controlled by an external conversion clock. Each of the conversion periods of the conversion clock is divided into a sampling phase and a bit-cycling phase. In the sampling phase, the SAR ADC needs to sample an analog input signal. And then, in the bit-cycling phase, the SAR ADC digit-by-digit generates digital output codes, corresponding to the analog input signal, from the most significant bit (MSB) to the least significant bit (LSB). Accordingly, a digital output signal is generated.
Prior to the next converting period, the SAR ADC has a period of idle time (i.e., the SAR ADC does not perform any action in the idle time). The length of the idle time is determined by the process, voltage, and temperature (PVT) variations, the noise, or other factors. In order to improve the efficiency of the SAR ADC, an SAR ADC with prolonged sampling phase is developed. In the SAR ADC having prolonged sampling phase, the starting time of the sampling phase is brought forward to the toggle timing of the last bit-cycling clock. However, in the TI SAR ADC architecture, overlapping of sampling phases between different ADCs occurs, so that the signals sampled by the sampling circuit of the SAR ADC are interfered, leading the reduction of sampling quality.